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| 1 S2002 dual serial backplane device october 9, 2000 / revision b S2002 ? dual serial backplane device device specification mac (asic) S2002 dual gigabit ethernet interface mac to serial backplane s2202 ge interface serial bp driver (asic) figure 1. typical dual gigabit ethernet application features ? broad operating rate range (.98 - 1.3 ghz) - 1062 mhz (fibre channel) - 1250 mhz (gigabit ethernet) line rates - 1/2 rate operation ? dual transmitter with phase-locked loop (pll) clock synthesis from low speed reference ? dual receiver pll provides clock and data recovery ? internally series terminated ttl outputs ? on-chip 8b/10b line encoding and decoding for two separate parallel 8-bit channels ? dual 8-bit parallel ttl interfaces with internal series terminated outputs ? low-jitter serial pecl interface ? individual local loopback control ? jtag 1149.1 boundary scan on low speed i/o signals ? interfaces with coax, twinax, or fiber optics ? single +3.3v supply, 1.85 w power dissipation ? compact 21mm x 21mm 156 tbga package applications ? ethernet backbones ? workstation ? frame buffer ? switched networks ? data broadcast environments ? proprietary extended backplanes general description the S2002 facilitates high-speed serial transmission of data in a variety of applications including gigabit ethernet, fibre channel, serial backplanes, and pro- prietary point to point links. the chip provides two separate transceivers which are operated individu- ally for a data capacity of >2 gbps. each bi-directional channel provides 8b/10b coding/ decoding, parallel to serial and serial to parallel con- version, clock generation/recovery, and framing. the on-chip transmit pll synthesizes the high-speed clock from a low-speed reference. the on-chip dual receive pll is used for clock recovery and data re- timing on the two independent data inputs. the transmitter and receiver each support differential pecl-compatible i/o for copper or fiber optic com- ponent interfaces with excellent signal integrity. lo- cal loopback mode allows for system diagnostics. the chip requires a 3.3v power supply and dissi- pates 1.85 watts. figure 1 shows the s2202 and S2002 in a gigabit ethernet application. figure 2 combines the S2002 with a crosspoint switch to demonstrate a serial backplane application. figure 3 is the input/ output diagram. figures 4 and 5 show the transmit and receive block diagrams, respectively.
2 dual serial backplane device S2002 october 9, 2000 / revision b figure 2. typical backplane application mac (asic) S2002 atm fibre channel ethernet etc. mac (asic) crosspoint switch s2016 s2025 mac (asic) S2002 atm fibre channel ethernet etc. mac (asic) mac (asic) S2002 atm fibre channel ethernet etc. mac (asic) mac (asic) S2002 atm fibre channel ethernet etc. mac (asic) backplane signal group 3 S2002 dual serial backplane device october 9, 2000 / revision b figure 3. S2002 input/output diagram refclk rate reset tclko sync txap/n txbp/n rxap/n rxbp/n dina[0:7] dna, kgena 10 dinb[0:7] dnb, kgenb 10 tclka tclkb 10 rca p/n 10 rcb p/n douta[0:7] eofa, kflaga doutb[0:7] eofb, kflagb clksel tmode erra errb lpena trs tms tck tdi tdo lpenb testmode testmode1 cmode 4 dual serial backplane device S2002 october 9, 2000 / revision b figure 4. transmitter block diagram 8b/10b encode 8 10 sync dna kgena dina[0:7] 8 dnb kgenb shift reg 8b/10b encode 8 10 dinb0:7] 8 shift reg tclkb din pll 10x/20x refclk clksel rate refclk tclko fifo (input) fifo (input) tclka txap txan txabp txbp txbn txbbp tmode 01 01 tmode 5 S2002 dual serial backplane device october 9, 2000 / revision b figure 5. receiver block diagram dout cru serial- parallel dout cru serial- parallel eofa kflaga erra douta[0:7] rxap rxan rxbp rxbn lpenb eofb kflagb errb doutb[0:7] q fifo (output) txbbp txabp refclk 8 8 rcap/n 2 rcbp/n 2 cmode rate fifo (output) 8 8 10 10 lpena tmode 8b/10b decode framing data stretching timing 8b/10b decode framing data stretching timing 6 dual serial backplane device S2002 october 9, 2000 / revision b transmitter description the transmitter section of the S2002 contains a single pll which is used to generate the serial rate transmit clock for all transmitters. two channels are provided with a variety of options regarding input clocking and loopback. the transmitters can operate in the range of .98 ghz to 1.3 ghz, 10 or 20 times the reference clock frequency. data input the S2002 has been designed to simplify the paral- lel interface data transfer and provides the utmost in flexibility regarding clocking of parallel data. the S2002 incorporates a unique fifo structure on both the parallel inputs and the parallel outputs which en- ables the user to provide a clean reference source for the pll and to accept a separate external clock which is used exclusively to reliably clock data into the device. data can also be clocked in using the refclk. data is input to each channel of the S2002 nominally as a 10 bit wide word. this consists of eight data bits of user data, kgen, and dn. an input fifo and a clock input, tclkx, are provided for each channel of the S2002. the device can operate in two different modes. the S2002 can be configured to use either the tclkx (tclk mode) input or the refclk input (refclk mode). in tclk or refclk mode, each byte of data is clocked into its fifo with the tclkx provided for each byte. table 1 provides a summary of the input modes for the S2002. operation in the tclk mode makes it easier for users to meet the relatively narrow setup and hold time window required by the parallel 10-bit interface. the tclk signal is used to clock the data into an internal holding register and the S2002 synchronizes its internal data flow to insure stable operation. how- ever, regardless of the clock mode, refclk is al- ways the vco reference clock. this facilitates the provision of a clean reference clock resulting in mini- mum jitter on the serial output. the tclk must be frequency locked to refclk, but may have an arbi- trary phase relationship. adjustment of internal tim- ing of the S2002 is performed during reset. once synchronized, the user must insure that the timing of the tclk signal does not change by more than 3 ns relative to the refclk. figure 6 demonstrates the flexibility afforded by the S2002. a low jitter reference is provided directly to the S2002 at either 1/10 or 1/20 the serial data rate. this insures minimum jitter in the synthesized clock used for serial data transmission. a system clock output at the parallel word rate, tclko, is derived from the pll and provided to the upstream circuit as a system clock. the frequency of this output is con- stant at the parallel word rate, 1/10 the serial data rate, regardless of whether the reference is provided at 1/10 or 1/20 the serial data rate. this clock can be buffered as required without concern about added delay. there is no phase requirement between tclko and tclkx, which is provided back to the S2002, other than that they remain within 3ns of the phase relationship established at reset. table 1. input modes e d o m tn o i t a r e p o 0 a t a d k c o l c o t d e s u k l c f e r . e d o m k l c f e r . s l e n n a h c l l a r o f s o f i f o t n i 1 o t n i a t a d k c o l c o t d e s u x k l c t . e d o m k l c t . s l e n n a h c l l a r o f s o f i f note that internal sychronization of fifos is performed upon de- assertion of reset or when the synchronization pattern is generated (sync = 1 dnx = 1). 7 S2002 dual serial backplane device october 9, 2000 / revision b figure 6. din data clocking with tclk the S2002 also supports the traditional refclk (tbc) clocking found in many fibre channel and gigabit ethernet applications and is illustrated in fig- ure 7. half rate operation the S2002 supports full and 1/2 rate operation for all modes of operation. when rate is low, the S2002 serial data rate equals the vco frequency. when rate is high, the vco is divided by 2 before being provided to the chip. thus the S2002 can support fibre channel and serial backplane functions at both full and 1/2 the vco rate. see table 5. 8b/10b coding the S2002 provides 8b/10b line coding for each channel. the 8b/10b transmission code includes se- rial encoding and decoding rules, special characters, and error control. information is encoded, 8 bits at a time, into a 10 bit transmission character. the char- acters defined by this code ensure that enough tran- sitions are present in the serial bit stream to make clock recovery possible at the receiver. the encod- ing also greatly increases the likelihood of detecting any single or multiple errors that might occur during the transmission and reception of data 1 . the 8b/10b transmission code includes d-charac- ters, used for data transmission, and k-characters, used for control or protocol functions. each d-char- acter and k-character has a positive and a negative parity version. the parity of each codeword is se- lected by the encoder to control the running disparity of the data stream. k-character generation is con- trolled individually for each channel using the kgenx input. when kgen is asserted, the data on the parallel input is mapped into the corresponding control character. the parity of the k-character is selected to minimize running disparity in the serial data stream. table 3 lists the k characters sup- ported by the S2002 and identifies the mapping of the din[7:0] bits to each character. refclk S2002 vco/10 or vco/20 tclkx dinx[0:7] ref oscillator mac asic tclko pll 1 1. a.x. widner and p.a. franaszek, "a byte-oriented dc bal- anced (0,4) 8b/10b transmission code," ibm research report rc9391, may 1982. figure 7. din clocking with refclk refclk S2002 tclkx dinx[0:7] ref oscillator mac asic tclko pll vco/10 8 dual serial backplane device S2002 october 9, 2000 / revision b in order to provide interface compatibility to non- amcc serial backplane transceivers, the S2002 can also generate a unique sync character consisting of 16 consecutive k28.5 characters. this event is initi- ated by the simultaneous assertion of sync and dn. the sync character may start with either a positive or negative parity k28.5. (depending on the current running disparity.) the parity of the second and third k28.5 are inverse with respect to a valid 8b/10b sequence. parity of the remaining k28.5 are 8b/10b compliant. thus the parity of the k28.5 pat- tern consists of + + - - + - + - + - + - + - + - or - - + + - + - + - + - + - + - +. table 2 identifies the S2002 transmit control signals. c n y sx n e g kx n dt u p t u o 2 0 0 2 s 000 . a t a d l e l l a r a p d e d o c n e 001 . r e t c a r a h c 5 . 8 2 k 011 d n a 3 e l b a t y b d e n i f e d s a r e t c a r a h c k . ] 0 : 7 [ n i d 1x1 d e t a r e n e g r e t c a r a h c c n y s d r o w 6 1 l a i c e p s . o f i f t i m s n a r t e h t s t e s e r d n a frequency synthesizer (pll) the S2002 synthesizes a serial transmit clock from the reference signal. upon startup, the S2002 will obtain phase and frequency lock within 2500 bit times after the start of receiving reference clock in- puts. reliable locking of the transmit pll is assured, but a lock-detect output is not provided. the special sync generation commences on the first cycle in which sync and dn=1 and continues for 16 cycles. during this period, the sync, kgen, and dn inputs are ignored (assertion of dn and sync during this period will not prolong or re-initial the special sync character generation). table 2. transmitter control signals 9 S2002 dual serial backplane device october 9, 2000 / revision b table 3. k character generation (dnx = 1 kgenx =1 sync = 0) k r e t c a r a h c ] 0 : 7 [ n i dn e g k + d r t n e r r u c- d r t n e r r u c s t n e m m o c j h g f i e d c b aj h g f i e d c b a 0 . 8 2 k 1 . 8 2 k 2 . 8 2 k 3 . 8 2 k 4 . 8 2 k 5 . 8 2 k 6 . 8 2 k 7 . 8 2 k 7 . 3 2 k 7 . 7 2 k 7 . 9 2 k 7 . 0 3 k 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 r e t c a r a h c c n y s table 4. data to 8b/10b alphabetic representation e t y b a t a d ] 9 : 0 [ t u o d r o ] 9 : 0 [ n i d 0123456789 b 0 1 / b 8 n o i t a t n e s e r p e r c i r e m u n a h p l a abcdei fghj table 5. operating rates reference clock input the reference clock input must be supplied with a low-jitter clock source. all reference clocks in a sys- tem must be within 200 ppm of each other to insure that the clock recovery units can lock to the serial data. the frequency of the reference clock must be either 1/10 the serial data rate, clksel = 0, or 1/20 the serial data rate, clksel=1. in both cases the fre- quency of the parallel word rate output, tclko, is constant at 1/10 the serial data rate. see table 5. serial data outputs the S2002 provides lvpecl level serial outputs. the serial outputs do not require output pulldown resistors. outputs are designed to perform optimally when ac-coupled. transmit fifo initialization the transmit fifo must be initialized after stable delivery of data and tclk to the parallel interface, and before entering the normal operational state of the circuit. fifo initialization is performed upon the de-assertion of the reset signal. the transmit fifo is also reset when the special synchronization pat- tern (sync=1, dn=1) is generated. tclko will op- erate normally regardless of the state of reset. e t a rl e s k l c k l c f e r y c n e u q e r f t u p t u o l a i r e s e t a r o k l c t y c n e u q e r f 00 0 1 / r d sz h g 3 . 1 C 8 9 . 00 1 / r d s 01 0 2 / r d sz h g 3 . 1 C 8 9 . 00 1 / r d s 10 0 1 / r d sz h g 5 6 . 0 C 9 4 . 00 1 / r d s 11 0 2 / r d sz h g 5 6 . 0 C 9 4 . 00 1 / r d s note: sdr = serial data rate 10 dual serial backplane device S2002 october 9, 2000 / revision b serial to parallel conversion once bit synchronization has been attained by the S2002 cru, the S2002 must synchronize to the 10 bit word boundary. word synchronization in the S2002 is accomplished by detecting and aligning to the 8b/10b k28.5 codeword. the S2002 will detect and byte-align to either polarity of the k28.5. each channel of the S2002 will detect and align to a k28.5 anywhere in the data stream. for tclk or refclk mode operation, the presence of a k28.5 is indicated for each channel by the assertion of the eofx sig- nal. table 7 details the function of the eof, kflag, and err pins in status reporting. k c o l t n e r r u c e t a t se t a t s e t a t s e t a t se t a t s y c n e u q e r f l l p ) k l c f e r . s v () k l c f e r . s v ( ) k l c f e r . s v ( ) k l c f e r . s v () k l c f e r . s v ( e t a t s k c o l w e n d e k c o l m p p 8 8 4 11 S2002 dual serial backplane device october 9, 2000 / revision b r r ef o eg a l f kn o i t p i r c s e dk n a r 00 0 . d e t c e t e d n e e b s a h r e t c a r a h c a t a d d i l a v a t a h t s e t a c i d n i . r e t c a r a h c l a m r o n 5 00 1 s a h 5 . 8 2 k n a h t r e h t o r e t c a r a h c k a t a h t s e t a c i d n i . ) 5 . 8 2 k t o n ( r e t c a r a h c k . d e t c e t e d n e e b 5 01 0 . d e s u t o n 01 1 n e e b s a h y t i r a p y r a r t i b r a f o r e t c a r a h c 5 . 8 2 k a t a h t s e t a c i d n i . - 5 . 8 2 k r o + 5 . 8 2 k . d e t c e t e d 3 10 0 x . x d d i l a v y n a o t g n i d n o p s e r r o c t o n d r o w a t a h t s e t a c i d n i . n o i t a l o i v d r o w e d o c . d e v i e c e r n e e b s a h g n i p p a m x . x k r o 2 10 1 . k c o l t i b u r c f o s s o l s e t a c i d n i , e d o m k l c f e r r o k l c t e h t n i n o i t a r e p o 1 11 0 . d e v r e s b o n e e b s a h r o r r e y t i r a p s i d g n i n n u r a t a h t s e t a c i d n i . r o r r e y t i r a p 4 11 1 . d e s u t o n table 7. error and status reporting 12 dual serial backplane device S2002 october 9, 2000 / revision b 8b/10b decoding after serial to parallel conversion, the S2002 pro- vides 8b/10b decoding of the data. the received 10- bit codeword is decoded to recover the original 8-bit data. the decoder also checks for errors and flags, either invalid codeword errors or running disparity errors by assertion of the errx signal. error type is determined by examining the eof output in accor- dance with table 7. when more than one reportable condition occurs simultaneously, reporting is in ac- cordance with the rank assigned by table 7. data output data is output on the dout[0:7] outputs. k-characters are flagged using the kflag signal. the eof (with kflag) is used to indicate the reception of a valid k28.5 character. invalid codewords and decoding er- rors are indicated on the err output. kflag, eof, and err are buffered with the data in the fifo to insure that all outputs are synchronized at the S2002 outputs. errors are reported independently for each channel in tclk or refclk mode operation. the S2002 ttl outputs are optimized to drive 65 w line impedances. internal source matching provides good performance on unterminated lines of reason- able length. parallel output clock rate two output clock modes are supported, as shown in table 8. when cmode is high, a complementary ttl clock at the data rate is provided on the rcxp/n outputs. data should be clocked on the rising edge of rcxp. when cmode is low, a complementary ttl clock at 1/2 the data rate is provided. data should be latched on the rising edge of rcxp and the rising edge of rcxn. in fibre channel and gigabit ethernet applications, multiple consecutive k28.5 characters cannot be generated. however, for serial backplane applica- tions this can occur. the S2002 must be able to operate properly when multiple k28.5 characters are received. after the first k28.5 is detected and aligned, the rcxp/n clock will operate without glitches or loss of cycles. receiver output clocking the S2002 parallel output clock source is deter- mined by the tmode selection. when refclk clocking is selected (tmode = low), the parallel output clocks (rcxp/n) are sourced from the tclka input. when tclk clocking is selected (external clocking mode), the parallel output clocks are de- rived from the recovered clock from each channel. table 8a describes the receiver output clocking op- tions available. when tclka is the output clock source, refclk and tclka must equal the parallel word rate (clksel = low). additionally, the recovered clocks and the clock input on tclka must be frequency locked in order to avoid overflow/underflow of the internal fifos. the propagation delay between tclka and doutx, listed in table 21, shows that the phase delay between tclka and the rcxp/n outputs may vary more than a bit time based on process variation. the recommended clocking configuration for exter- nal clocking mode (refclk input clocking) is shown in figure 9. tclka is sourced from tclko, which is frequency locked to the reference clock input. 13 S2002 dual serial backplane device october 9, 2000 / revision b figure 8. S2002 diagnostic loopback operation cru csu other operating modes operating frequency range the S2002 is designed to operate at serial baud rates of .98 ghz to 1.3 ghz (800 mbps to 1040 mbps user data rate). the part is specified at fibre channel (1062 mhz) and gigabit ethernet (1.25 ghz) serial baud rates, but will operate satisfactorily at any rate in this range. loopback mode when loopback mode is enabled, the serial data from the transmitter is provided to the serial input of the receiver, as shown in figure 8. this provides the ability to perform system diagnostics and off-line testing of the interface to verify the integrity of the serial channel. loopback mode is enabled indepen- dently for each channel using its respective loopback-enable input, lpen. test modes the reset pin is used to initialize the transmit fifos and must be asserted (low) prior to entering the normal operational state (see section transmit fifo initialization). note: serial output data remains active during loopback opera- tion to enable other system tests to be performed. e d o me d o m cq e r f n / p x c r e d o m k c o l c f l a h00 2 / o c v e d o m k c o l c l l u f10 1 / o c v table 8. output clock mode table 8a. S2002 data clocking e d o m t k c o l c t u p n i e c r u o s k c o l c t u p t u o e c r u o s 0k l c f e ra k l c t 1x k l c tx c r refclk serdes tclka ref oscillator controller/mac asic/fpga tclko pll parallel data rcxp/n 2 recovered clock figure 9. external receiver clocking 14 dual serial backplane device S2002 october 9, 2000 / revision b jtag testing the jtag implementation for the S2002 is compli- ant with the ieee1149.1 requirements. jtag is used to test the connectivity of the pins on the chip. the tap, (test access port), provides access to the test logic of the chip. when trst is asserted the tap is initialized. tap is a state machine that is controlled by tms. the test instruction and data are loaded through tdi on the rising edge of tck. when tms is high the test instruction is loaded into the instruction register. when tms is low the test data is loaded into the data register. tdo changes on the falling edge of tck. all input pins, including clocks, that have boundary scan are observe only. they can be sampled in either normal operational or test mode. all output pins that have boundary scan, are observe and control. they can be sampled as they are driven out of the chip in normal operational mode, and they can be driven out of the chip in test mode using the extest instruction. since jtag testing operates only on digital signals there are some pins with analog signals that jtag does not cover. the jtag imple- mentation has the three required instruction, bypass, extest, and sample/preload. instruction code bypass 11 extest 00 sample/preload 01 id code 10 jtag instruction description: the bypass register contains a single shift-register stage and is used to provide a minimum-length serial path between the tdi and tdo pins of a component when no test operation of that component is re- quired. this allows more rapid movement of test data to and from other components on a board that are required to perform test operations. the extest instruction allows testing of off-chip cir- cuitry and board level interconnections. data would typically be loaded onto the latched parallel outputs of boundary-scan shift-register stages using the sample/preload instruction prior to selection of the extest instruction. the sample/preload instruction allows a snap- shot of the normal operation of the component to be taken and examined. it also allows data values to be loaded onto the latched parallel outputs of the boundary-scan shift register prior to selection of the other boundary-scan test instructions. the following table provides a list of the pins that are jtag tested. each port has a boundary scan regis- ter (bsr), unless otherwise noted. the following fea- tures are described: the jtag mode of each register (input, output2, or internal (refers to an internal pack- age pin)), the direction of the port if it has a bound- ary scan register (in or out), and the position of this register on the scan chain. 15 S2002 dual serial backplane device october 9, 2000 / revision b table 9. jtag pin assignments 2 0 0 2 s e m a n n i p n a c s _ e r o c e m a n t r o p g a t j e d o m g n i t u o r t u o n i c n y sc n y st u p n i0- e d o m ce d o m ct u p n i1- e d o m t s e t0 _ e d o m t s e tt u p n i2- l a n r e t n i3- b n e p lb n e p lt u p n i4- l a n r e t n i5- a n e p la n e p lt u p n i6- l e s k l cl e s k l ct u p n i7- e d o m te d o m tt u p n i8- l a n r e t n i9- t e s e rt e s e rt u p n i0 1- k l c f e rk l c f e rt u p n i1 1- o k l c t _ k l c _ t i m s n a r t t u o _ f u b 2 t u p t u o-2 1 l a n r e t n i2 2 - 3 1- 1 e d o m t s e t1 _ e d o m t s e tt u p n i3 2- b n db n dt u p n i4 2- b n e g kb n e g kt u p n i5 2- 7 b n i d) 7 ( b _ n i a t a d tt u p n i6 2- 6 b n i d) 6 ( b _ n i a t a d tt u p n i7 2- 5 b n i d) 5 ( b _ n i a t a d tt u p n i8 2- 4 b n i d) 4 ( b _ n i a t a d tt u p n i9 2- 3 b n i d) 3 ( b _ n i a t a d tt u p n i0 3- 2 b n i d) 2 ( b _ n i a t a d tt u p n i1 3- 1 b n i d) 1 ( b _ n i a t a d tt u p n i2 3- 0 b n i d) 0 ( b _ n i a t a d tt u p n i3 3- b k l c tb k l c tt u p n i4 3- l a n r e t n i5 4 - 5 3- a n da n dt u p n i6 4- a n e g ka n e g kt u p n i7 4- 7 a n i d) 7 ( a _ n i a t a d tt u p n i8 4- 6 a n i d) 6 ( a _ n i a t a d tt u p n i9 4- 5 a n i d) 5 ( a _ n i a t a d tt u p n i0 5- 4 a n i d) 4 ( a _ n i a t a d tt u p n i1 5- 3 a n i d) 3 ( a _ n i a t a d tt u p n i2 5- 2 a n i d) 2 ( a _ n i a t a d tt u p n i3 5- 1 a n i d) 1 ( a _ n i a t a d tt u p n i4 5- 0 a n i d) 0 ( a _ n i a t a d tt u p n i5 5- a k l c ta k l c tt u p n i6 5- l a n r e t n i-9 6 - 7 5 p b c rp b c r2 t u p t u o-0 7 n b c rn b c r2 t u p t u o-1 7 7 b t u o d) 7 ( b _ t u o a t a d r2 t u p t u o-2 7 6 b t u o d) 6 ( b _ t u o a t a d r2 t u p t u o-3 7 5 b t u o d) 5 ( b _ t u o a t a d r2 t u p t u o-4 7 4 b t u o d) 4 ( b _ t u o a t a d r2 t u p t u o-5 7 3 b t u o d) 3 ( b _ t u o a t a d r2 t u p t u o-6 7 2 0 0 2 s e m a n n i p n a c s _ e r o c e m a n t r o p g a t j e d o m g n i t u o r t u o n i 2 b t u o d) 2 ( b _ t u o a t a d r2 t u p t u o-7 7 1 b t u o d) 1 ( b _ t u o a t a d r2 t u p t u o-8 7 0 b t u o d) 0 ( b _ t u o a t a d r2 t u p t u o-9 7 b r r eb _ d r r e2 t u p t u o-0 8 b f o eb _ d f o e2 t u p t u o-1 8 b g a l f kb _ d g a l f k2 t u p t u o-2 8 l a n r e t n i-5 9 - 3 8 p a c rp a c r2 t u p t u o-6 9 n a c rn a c r2 t u p t u o-7 9 a r r ea _ d r r e2 t u p t u o-8 9 7 a t u o d) 7 ( a _ t u o a t a d r2 t u p t u o-9 9 6 a t u o d) 6 ( a _ t u o a t a d r2 t u p t u o-0 0 1 5 a t u o d) 5 ( a _ t u o a t a d r2 t u p t u o-1 0 1 4 a t u o d) 4 ( a _ t u o a t a d r2 t u p t u o-2 0 1 3 a t u o d) 3 ( a _ t u o a t a d r2 t u p t u o-3 0 1 2 a t u o d) 2 ( a _ t u o a t a d r2 t u p t u o-4 0 1 1 a t u o d) 1 ( a _ t u o a t a d r2 t u p t u o-5 0 1 0 a t u o d) 0 ( a _ t u o a t a d r2 t u p t u o-6 0 1 a f o ea _ d f o e2 t u p t u o-7 0 1 a g a l f ka _ d g a l f k2 t u p t u o-8 0 1 l a n r e t n i-9 0 1 s n i p l o r t n o c g a t j ) r e t s i g e r n a c s y r a d n u o b a e v a h t o n o d t a h t s t r o p ( k c tk c t _ g a t j--- i d ti d t _ g a t j--- o d to d t _ g a t j--- s m ts m t _ g a t j--- s r ts r t _ g a t j--- d e t s e t g a t j t o n s n i p p a x t---- n a x t---- p b x t---- n b x t---- e t a r---- p a x r---- n a x r---- p b x r---- n b x r---- 16 dual serial backplane device S2002 october 9, 2000 / revision b e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 7 a n i d 6 a n i d 5 a n i d 4 a n i d 3 a n i d 2 a n i d 1 a n i d 0 a n i d l t ti 2 1 p 4 1 t 2 1 r 1 1 p 3 1 t 1 1 r 2 1 t 0 1 p d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . a l e n n a h c r o f a t a d t i m s n a r t . k l c f e r r o a k l c t f o e g d e g n i s i r e h t n o n i a n dl t ti 5 1 tb 0 1 / b 8 s i ] 7 : 0 [ a n i d n o t n e s e r p a t a d , w o l n e h w . t o n _ a t a d l a i c e p s , h g i h n e h w . y l l a i r e s d e t t i m s n a r t d n a d e d o c n e . 2 e l b a t n i d e t a c i d n i s a d e t a r e n e g e r a s e c n e u q e s / r e t c a r a h c a n e g kl t ti 3 1 rn o a t a d e h t s e s u a c h g i h a n e g k . n o i t a r e n e g r e t c a r a h c - k ) . 2 e l b a t e e s ( . r e t c a r a h c - k a o t n i d e d o c n e e b o t ] 7 : 0 [ a n i d a k l c tl t ti 0 1 rd e s u s i l a n g i s s i h t , h g i h s i e d o m t n e h w . a k c o l c a t a d t i m s n a r t . 2 0 0 2 s e h t o t n i a n d d n a , a n e g k , ] 7 : 0 [ a n i d n o a t a d k c o l c o t . d e r o n g i s i a k l c t , w o l s i e d o m t n e h w 7 b n i d 6 b n i d 5 b n i d 4 b n i d 3 b n i d 2 b n i d 1 b n i d 0 b n i d l t ti 5 1 m 4 1 m 6 1 n 5 1 n 4 1 n 6 1 p 5 1 p 6 1 r n i d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . b l e n n a h c r o f a t a d t i m s n a r t . k l c f e r r o b k l c t f o e g d e g n i s i r e h t n o b n dl t ti 4 1 lb 0 1 / b 8 s i ] 7 : 0 [ b n i d n o t n e s e r p a t a d , w o l n e h w . t o n _ a t a d l a i c e p s , h g i h n e h w . y l l a i r e s d e t t i m s n a r t d n a d e d o c n e . 2 e l b a t n i d e t a c i d n i s a d e t a r e n e g e r a s e c n e u q e s / r e t c a r a h c b n e g kl t ti 6 1 mn o a t a d e h t s e s u a c h g i h b n e g k . n o i t a r e n e g r e t c a r a h c - k ) . 2 e l b a t e e s ( . r e t c a r a h c - k a o t n i d e d o c n e e b o t ] 7 : 0 [ b n i d b k l c tl t ti 4 1 pd e s u s i l a n g i s s i h t , h g i h s i e d o m t n e h w . b k c o l c a t a d t i m s n a r t . 2 0 0 2 s e h t o t n i b n d d n a , b n e g k , ] 7 : 0 [ b n i d n o a t a d k c o l c o t . d e r o n g i s i b k l c t , w o l s i e d o m t n e h w c n y sl t ti4 ce c n e u q e s l a i c e p s a e t a r e n e g o t d e s u ) 2 e l b a t e e s ( , h g i h n e h w . t x e t r e i l r a e e e s . s r e t c a r a h c 5 . 8 2 k f o table 10. transmitter input pin assignment and descriptions 17 S2002 dual serial backplane device october 9, 2000 / revision b table 12. mode control signals e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d e d o m t s e tl t ti3 d. n o i t a r e p o l a m r o n r o f w o l p e e k . l o r t n o c e d o m t s e t 1 e d o m t s e tl t ti 5 1 l. n o i t a r e p o l a m r o n r o f w o l p e e k . l o r t n o c e d o m t s e t e d o m tl t ti 3 1 ao t d e s u k c o l c e h t f o e c r u o s e h t s l o r t n o c . l o r t n o c e d o m r e f s n a r t s i e d o m t n e h w . 2 0 0 2 s e h t m o r f d n a o t a t a d t u p t u o d n a t u p n i , c n y s , x n d , ] 7 : 0 [ x n i d n o a t a d k c o l c o t d e s u s i k l c f e r , w o l l e l l a r a p k c o l c o t d e s u s i a k l c t . 2 0 0 2 s e h t o t n i x n e g k d n a . e c i v e d e h t f o t u o x g a l f k d n a , x r r e , x f o e , ] 7 : 0 [ x t u o d a t a d a t a d k c o l c o t d e s u e r a s t u p n i x k l c t e h t , h g i h s i e d o m t n e h w d e v i r e d e r a s k c o l c t u p t u o e h t . s l e n n a h c e v i t c e p s e r r i e h t o t n i . s u r c ' s r e v i e c e r e h t m o r f l e s k l cl t ti 1 1 be h t r o f l l p e h t s e r u g i f n o c l a n g i s s i h t . t u p n i t c e l e s k l c f e r e h t , 0 = l e s k l c n e h w . y c n e u q e r f k l c f e r e t a i r p o r p p a n e h w . e t a r d r o w l e l l a r a p e h t s l a u q e y c n e u q e r f k l c f e r a t a d l e l l a r a p e h t 2 / 1 s i y c n e u q e r f k l c f e r e h t , 1 = l e s k l c . e t a r k l c f e rl t ti 4 1 jy c n e u q e r f d n a o c v t i m s n a r t e h t r o f d e s u s i k c o l c e c n e r e f e r . a t a d l a i r e s r e v i e c e r e h t m o r f d e r e v o c e r k c o l c e h t r o f k c e h c t e s e rl t ti 5 1 bd e c r o f s i l l p r e v i e c e r e h t . t e s e r n i d l e h s i 2 0 0 2 s e h t , w o l n e h w e g d e g n i s i r e h t n o d e z i l a i t i n i e r a s o f i f e h t . k l c f e r e h t o t k c o l o t . y l l a m r o n s e t a r e p o 2 0 0 2 s e h t , h g i h n e h w . t e s e r f o e t a rl t ti 1 1 cl a u q e e t a r t u p t u o l a i r e s e h t h t i w s e t a r e p o 2 0 0 2 s e h t , w o l n e h w e h t h t i w s e t a r e p o 2 0 0 2 s e h t , h g i h n e h w . y c n e u q e r f o c v e h t o t . s n o i t c n u f l l a r o f 2 y b d e d i v i d y l l a n r e t n i o c v note: all ttl inputs except refclk have internal pull-up networks. table 11. transmitter output signals e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p a x t n a x t . f f i d l c e p v l o6 1 d 6 1 e . a l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h p b x t n b x t . f f i d l c e p v l o6 1 g 6 1 f . b l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h o k l c tl t to 5 1 kd e d i v o r p s i k c o l c s i h t . e t a r a t a d l e l l a r a p e h t t a k c o l c t u p t u o l t t . y r t i u c r i c m a e r t s - p u y b e s u r o f 18 dual serial backplane device S2002 october 9, 2000 / revision b table 13. receiver output pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 7 a t u o d 6 a t u o d 5 a t u o d 4 a t u o d 3 a t u o d 2 a t u o d 1 a t u o d 0 a t u o d l t to2 l 1 l 2 k 1 k 3 j 1 j 3 h 2 h d i l a v s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r a l e n n a h c e h t n o d i l a v d n a e d o m k c o l c l l u f n i p a c r f o e g d e g n i s i r e h t n o . e d o m k c o l c f l a h n i n a c r d n a p a c r h t o b f o e g d e g n i s i r a f o el t to1 gs e t a c i d n i t u p t u o s i h t n o h g i h a . d e t c e t e d e m a r f f o d n e a l e n n a h c l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b s a h 5 . 8 2 k d i l a v a t a h t . ] 7 : 0 [ a t u o d s t u p t u o a t a d a g a l f kl t to2 ga t a h t s e t a c i d n i a g a l f k n i h g i h a . g a l f r e t c a r a h c - k a l e n n a h c e h t n o t n e s e r p a t a d . d e t c e t e d n e e b s a h r e t c a r a h c l o r t n o c d i l a v h c i h w e t a c i d n i o t d e s u e b d l u o h s ] 7 : 0 [ a t u o d e c a f r e t n i l e l l a r a p . d e v i e c e r s a w r e t c a r a h c a r r el t to2 je h t s e i f i n g i s a r r e n o h g i h a . r o r r e e v i e c e r a l e n n a h c r o r r e d r o w e d o c d i l a v n i n a r o r o r r e y t i r a p a r e h t i e f o e c n e r r u c c o . a t a d d e v i e c e r e h t f o g n i d o c e d g n i r u d p a c r n a c r l t to1 m 3 l , a f o e , ] 7 : 0 [ a t u o d , a t a d e v i e c e r l e l l a r a p . k c o l c a t a d e v i e c e r n e h w p a c r f o e g d e g n i s i r e h t n o d i l a v e r a a r r e d n a , a g a l f k d n a p a c r h t o b f o e g d e g n i s i r e h t n o d i l a v d n a e d o m k c o l c l l u f n i . e d o m k c o l c f l a h n i n a c r 7 b t u o d 6 b t u o d 5 b t u o d 4 b t u o d 3 b t u o d 2 b t u o d 1 b t u o d 0 b t u o d l t to8 p 5 t 6 r 6 p 5 r 3 t 5 p 3 r d i l a v s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r b l e n n a h c e h t n o d i l a v d n a e d o m k c o l c l l u f n i p b c r f o e g d e g n i s i r e h t n o . e d o m k c o l c f l a h n i n b c r d n a p b c r h t o b f o e g d e g n i s i r b f o el t to3 ps e t a c i d n i t u p t u o s i h t n o h g i h a . d e t c e t e d e m a r f f o d n e b l e n n a h c l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b s a h 5 . 8 2 k d i l a v a t a h t . ] 7 : 0 [ b t u o d s t u p t u o a t a d b g a l f kl t to2 pa t a h t s e t a c i d n i b g a l f k n i h g i h a . g a l f r e t c a r a h c - k b l e n n a h c e h t n o t n e s e r p a t a d . d e t c e t e d n e e b s a h r e t c a r a h c l o r t n o c d i l a v h c i h w e t a c i d n i o t d e s u e b d l u o h s ] 7 : 0 [ b t u o d e c a f r e t n i l e l l a r a p . d e v i e c e r s a w r e t c a r a h c b r r el t to4 pe h t s e i f i n g i s b r r e n o h g i h a . r o r r e e v i e c e r b l e n n a h c r o r r e d r o w e d o c d i l a v n i n a r o r o r r e y t i r a p a r e h t i e f o e c n e r r u c c o . a t a d d e v i e c e r e h t f o g n i d o c e d g n i r u d p b c r n b c r l t to7 r 7 p , b f o e , ] 7 : 0 [ b t u o d , a t a d e v i e c e r l e l l a r a p . k c o l c a t a d e v i e c e r n e h w p b c r f o e g d e g n i s i r e h t n o d i l a v e r a b r r e d n a , b g a l f k d n a p b c r h t o b f o e g d e g n i s i r e h t n o d i l a v d n a e d o m k c o l c l l u f n i . e d o m k c o l c f l a h n i n b c r 19 S2002 dual serial backplane device october 9, 2000 / revision b table 16. power and ground signals table 14. receiver input pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p a x r n a x r . f f i d l c e p v l i3 a 4 a e h t s i p a x r . a l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d d d v o t d e s a i b y l l a n r e t n i . e v i t a g e n e h t s i n a x r , t u p n i e v i t i s o p . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - p b x r n b x r . f f i d l c e p v l i8 a 9 a e h t s i p b x r . b l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d d d v o t d e s a i b y l l a n r e t n i . e v i t a g e n e h t s i n b x r , t u p n i e v i t i s o p . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - table 15. receiver control signals e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d a n e p l b n e p l l t ti 4 1 c 4 1 h l a i r e s d e e p s h g i h e h t s i e c r u o s t u p n i , w o l n e h w . e l b a n e k c a b p o o l h c a e r o f t u p t u o l a i r e s e h t , h g i h n e h w . l e n n a h c h c a e r o f t u p n i . t u p n i s t i o t k c a b d e p o o l s i l e n n a h c e d o m cl t ti2 cs k c o l c t u p t u o l e l l a r a p e h t , w o l n e h w . l o r t n o c e d o m k c o l c l e l l a r a p e h t , h g i h n e h w . e t a r a t a d e h t 2 / 1 o t l a u q e s i e t a r ) n / p x c r ( . e t a r a t a d e h t o t l a u q e s i e t a r ) n / p x c r ( s k c o l c t u p t u o note: all ttl inputs except refclk have internal pull-up networks. e m a n n i p. y t q# n i pn o i t p i r c s e d a d d v4, 4 b , 6 a 8 c , 3 1 b . e s i o n w o l ) d d v ( r e w o p g o l a n a a s s v3, 8 b , 2 a 3 1 c . ) s s v ( d n u o r g g o l a n a d d v3, 6 c , 2 1 b 9 c . ) d d v ( y r t i u c r i c d e e p s h g i h r o f r e w o p s s v b u s s s v 8, 1 1 a , 7 a , 4 1 a , 2 1 a , 7 b , 5 b 2 1 c , 7 c . ) s s v ( y r t i u c r i c d e e p s h g i h r o f d n u o r g 20 dual serial backplane device S2002 october 9, 2000 / revision b e m a n n i p. y t q# n i pn o i t p i r c s e d r w p l c e p4, 5 1 f , 5 1 d 5 1 h , 4 1 g ) d d v ( r e w o p l c e p d n g l c e p26 1 c 6 1 j ) s s v ( d n u o r g l c e p r w p g i d6, 1 c , 2 b , 5 1 j , 2 d 9 p , 1 n ) d d v ( r e w o p y r t i u c r i c e r o c d n g g i d8, 1 d , 3 c , 3 e , 2 e , 1 r , 6 1 k 1 1 t , 1 t ) s s v ( d n u o r g y r t i u c r i c e r o c r w p l t t8, 3 g , 1 f , 2 m , 1 h , 4 r , 1 p 7 t , 8 r ) d d v ( o / i l t t r o f r e w o p d n g l t t0 1, 2 f , 1 e , 3 k , 3 f , 3 n , 3 m , 2 t , 2 r 8 t , 4 t ) s s v ( o / i l t t r o f d n u o r g r w p16 1 ar e w o p d n g6, 4 1 k , 1 b , 3 1 p , 6 1 l 6 1 t , 4 1 r d n u o r g 1 p a c 2 p a c 25 1 a 4 1 b r o t i c a p a c r e t l i f p o o l l a n r e t x e r o f s n i p c n8 1, 5 a , 1 a , 9 b , 6 b , 5 c , 6 1 b , 4 1 d , 5 1 c , 5 1 e , 4 1 e , 5 1 g , 4 1 f , 9 r , 2 n , 6 t , 5 1 r 0 1 t , 9 t . t c e n n o c t o n o d . s n i p t s e t s a d e s u . d e t c e n n o c t o n table 16. power and ground signals (continued) 21 S2002 dual serial backplane device october 9, 2000 / revision b e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d s m tl t ti0 1 a. e c i v e d f o g n i t s e t g a t j s e l b a n e . t c e l e s e d o m t s e t k c tl t ti0 1 b. k c o l c t s e t g a t j . k c o l c t s e t i d tl t ti0 1 c. t u p n i a t a d g a t j . n i a t a d t s e t o d tl t t o e t a t s i r t 6 1 h e c n a d e p m i h g i h e b n a c . t u p t u o a t a d g a t j . t u o a t a d t s e t . d n a m m o c r e l l o r t n o c g a t j r e d n u s r tl t ti3 b. e n i h c a m e t a t s t s e t g a t j s t e s e r . t e s e r t s e t table 17. jtag test signals 22 dual serial backplane device S2002 october 9, 2000 / revision b figure 10. S2002 pinout (bottom view) a b c d e f g h j k l m n p r t 1 c nd n gr w p g i dd n g g i dd n g l t tr w p l t ta f o er w p l t t2 a t u o d4 a t u o d6 a t u o dp a c rr w p g i dr w p l t td n g g i dd n g g i d 2 a s s vr w p g i de d o m cr w p g i dd n g g i dd n g l t ta g a l f k0 a t u o da r r e5 a t u o d7 a t u o dr w p l t tc nb g a l f kd n g l t td n g l t t 3 p a x rs r td n g g i d t s e t e d o m d n g g i dd n g l t tr w p l t t1 a t u o d3 a t u o dd n g l t tn a c rd n g l t td n g l t tb f o e0 b t u o d2 b t u o d 4 n a x ra d d vc n y s b r r er w p l t td n g l t t 5 c nb u s s s vc n 1 b t u o d3 b t u o d6 b t u o d 6 a d d vc nd d v 4 b t u o d5 b t u o dc n 7 b u s s s vs s vs s v n b c rp b c rr w p l t t 8 p b x ra s s va d d v 7 b t u o dr w p l t td n g l t t 9 n b x rc nd d v r w p g i dc nc n 0 1 s m tk c ti d t 0 a n i da k l c tc n 1 1 s s vl e s k l ce t a r 4 a n i d2 a n i dd n g g i d 2 1 b u s s s vd d vb u s s s v 7 a n i d5 a n i d1 a n i d 3 1 e d o m ta d d va s s v d n ga n e g k3 a n i d 4 1 s s v2 p a ca n e p lc nc nc n l c e p r w p b n e p lk l c f e rd n gb n d6 b n i d3 b n i db k l c td n g6 a n i d 5 1 1 p a ct e s e rc n l c e p r w p c n l c e p r w p c n l c e p r w p r w p g i do k l c t t s e t 1 e d o m 7 b n i d4 b n i d1 b n i dc na n d 6 1 r w pc nd n g l c e pp a x tn a x tn b x tp b x to d td n g l c e pd n g g i dd n gb n e g k5 b n i d2 b n i d0 b n i dd n g note: nc used as test pins. do not connect. 23 S2002 dual serial backplane device october 9, 2000 / revision b figure 11. S2002 pinout (top view) t r p n m l k j h g f e d c b a d n g g i dd n g g i dr w p l t tr w p g i dp a c r6 a t u o d4 a t u o d2 a t u o dr w p l t ta f o er w p l t td n g l t td n g g i dr w p g i dd n gc n 1 d n g l t td n g l t tb g a l f kc nr w p l t t7 a t u o d5 a t u o da r r e0 a t u o da g a l f kd n g l t td n g g i dr w p g i de d o m cr w p g i da s s v 2 2 b t u o d0 b t u o db f o ed n g l t td n g l t tn a c rd n g l t t3 a t u o d1 a t u o dr w p l t td n g l t td n g g i d t s e t e d o m d n g g i ds r tp a x r 3 d n g l t tr w p l t tb r r e c n y sa d d vn a x r 4 6 b t u o d3 b t u o d1 b t u o d c nb u s s s vc n 5 c n5 b t u o d4 b t u o d d d vc na d d v 6 r w p l t tp b c rn b c r s s vs s vb u s s s v 7 d n g l t tr w p l t t7 b t u o d a d d va s s vp b x r 8 c nc nr w p g i d d d vc nn b x r 9 c na k l c t0 a n i d i d tk c ts m t 0 1 d n g g i d2 a n i d4 a n i d e t a rl e s k l cs s v 1 1 1 a n i d5 a n i d7 a n i d b u s s s vd d vb u s s s v 2 1 3 a n i da n e g kd n g a s s va d d ve d o m t 3 1 6 a n i dd n gb k l c t3 b n i d6 b n i db n dd n gk l c f e rb n e p l l c e p r w p c nc nc na n e p l2 p a cs s v 4 1 a n dc n1 b n i d4 b n i d7 b n i d t s e t 1 e d o m o k l c tr w p g i d l c e p r w p c n l c e p r w p c n l c e p r w p c nt e s e r1 p a c 5 1 d n g0 b n i d2 b n i d5 b n i db n e g kd n gd n g g i dd n g l c e po d tp b x tn b x tn a x tp a x td n g l c e pc nr w p 6 1 note: nc used as test pins. do not connect. 24 dual serial backplane device S2002 october 9, 2000 / revision b figure 12. compact 21mm x 21mm 156 tbga package e c i v e d q ) r i a l l i t s ( a j q c j 2 0 0 2 sw / c ? 8 . 9 1w / c ? 5 . 3 thermal management 25 S2002 dual serial backplane device october 9, 2000 / revision b tclkx dinx[0:7], dnx, kgenx, sync t 1 t 2 serial data out figure 14. transmitter timing (tclk mode, tmode = 1) table 19. S2002 transmitter timing (tclk mode, tmode = 1) 1. all ac measurements are made from the reference voltage levels of the clock (1.4v) to the valid input or output data levels (.8v or 2.0v). s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 1 k l c t . t . r . w p u t e s a t a d0 . 1-s n. 1 e t o n e e s t 2 k l c t . t . r . w d l o h a t a d5 . 0-s n d n a x k l c t n e e w t e b t f i r d e s a h p k l c f e r 3 -3 +s n figure 13. transmitter timing (refclk mode, tmode = 0) refclk dinx[0:7], dnx, kgenx, sync t 1 t 2 serial data out s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 1 k l c f e r . t . r . w p u t e s a t a d5 . 0-s n. 1 e t o n e e s t 2 k l c f e r . t . r . w d l o h a t a d5 . 1-s n table 18. S2002 transmitter timing (refclk mode, tmode = 0) 1. all ac measurements are made from the reference voltage levels of the clock (1.4v) to the valid input or output data levels (.8v or 2.0v). 26 dual serial backplane device S2002 october 9, 2000 / revision b s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 3 n / p x c r . t . r . w p u t e s a t a d 5 . 2 0 . 3 s n s p b g 5 2 . 1 t a s p b g 2 6 0 . 1 t a 2 , 1 1 = e d o m t t 4 n / p x c r . t . r . w d l o h a t a d5 . 2s n1 = e d o m t t 5 n / p x c r . t . r . w p u t e s a t a d 5 . 2 0 . 3 s n s p b g 5 2 . 1 t a s p b g 2 6 0 . 1 t a 2 , 1 1 = e d o m t t 6 n / p x c r . t . r . w d l o h a t a d5 . 2s n1 = e d o m t t 7 o t e s i r p x c r m o r f e m i t e s i r n x c r 5 . 7 9 . 8 5 . 8 9 . 9 s n s n s p b g 5 2 . 1 t a s p b g 2 6 0 . 1 t a 2 , 1 t p r t , p f s e m i t l l a f d n a e s i r p x c r4 . 2s n . 2 e t o n e e s . 0 2 e r u g i f e e s t n r t , n f s e m i t l l a f d n a e s i r n x c r4 . 2s n . 2 e t o n e e s . 0 2 e r u g i f e e s t r d t , f d s e m i t l l a f d n a e s i r x t u o d4 . 2s n . 2 e t o n e e s . 0 2 e r u g i f e e s e l c y c y t u de l c y c y t u d n / p x c r0 40 6% . 1 e t o n e e s table 20. S2002 receiver timing (full and half clock mode) 1. measurements made from the reference voltage levels of the clock (1.4v) to the valid input or output data levels (.8v or 2.0v). 2. ttl/cmos ac timing measurements are assumed to have an output load of 10pf. table 21. S2002 receiver timing (external clock mode) 1. measurements made from the reference voltage levels of the clock (1.4v) to the valid input or output data levels (.8v or 2.0 v). s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 8 x t u o d o t a k l c t y a l e d n o i t a g a p o r p 0 . 30 . 8s n e h t t a e c n a t i c a p a c d a o l f p 0 1 0 5 h c n i 3 a f o d n e w . e n i l n o i s s i m s n a r t 27 S2002 dual serial backplane device october 9, 2000 / revision b figure 16. receiver timing (half clock mode, cmode = 0, tmode = 1) figure 15. receiver timing (full clock mode, cmode = 1) rcxn doutx[0:7], eofx, kflagx, errx serial data in t 3 t 4 rcxp rcxn doutx[0:7], eofx, kflagx, errx serial data in rcxp t 5 t 6 t 7 t 5 t 6 figure 17. receiver timing (external clock mode) (tclka to data propagation delay, tmode = 0) doutx[0:7], eofx, kflagx, errx serial data in t 8 tclka (input) 28 dual serial backplane device S2002 october 9, 2000 / revision b note: measurements are made at 1.4v level of clocks. table 22. S2002 transmitter (tclko timing) figure 18. tclko timing refclk t 9 tclko s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 9 k l c f e r . t . r . w o k l c t0 . 15 . 6s n e l c y c y t u d o k l c t% 5 4% 5 5% 29 S2002 dual serial backplane device october 9, 2000 / revision b r e t e m a r a pn i mp y tx a ms t i n u e r u t a r e p m e t e g a r o t s5 6 -0 5 1c ? d n g o t t c e p s e r h t i w d d v n o e g a t l o v5 . 0 -0 . 5 +v n i p t u p n i l t t y n a n o e g a t l o v5 . 0 -7 4 . 3v n i p t u p n i l c e p y n a n o e g a t l o v0d d vv t n e r r u c k n i s t u p t u o l t t8a m t n e r r u c e c r u o s t u p t u o l t t8a m t n e r r u c e c r u o s t u p t u o l c e p d e e p s h g i h5 2a m y t i v i t i s n e s d s e 1 v 0 0 5 r e v o r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t t n e i b m a00 7c ? s a i b r e d n u e r u t a r e p m e t n o i t c n u j0 3 1c ? o t t c e p s e r h t i w n i p r e w o p y n a n o e g a t l o v s s v / d n g 3 1 . 33 . 37 4 . 3v n i p t u p n i l t t y n a n o e g a t l o v07 4 . 3v n i p t u p n i l c e p y n a n o e g a t l o v d d v v 2 - d d vv s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t fe c n a r e l o t y c n e u q e r f0 0 1 -0 0 1 +m p p d t 2 - 1 y r t e m m y s0 40 6% . t p % 0 5 t a e l c y c y t u d t r c r t , f c r e m i t l l a f d n a e s i r k l c f e r2s n. % 0 8 - % 0 2 r e t t i j0 8s p n i a t n i a m o t , k a e p - o t - k a e p 3 . g n i n e p o e y e % 7 7 table 23. absolute maximum ratings table 24. recommended operating conditions table 25. reference clock requirements 1. human body model. 30 dual serial backplane device S2002 october 9, 2000 / revision b s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v h o ) l t t ( e g a t l o v h g i h t u p t u o4 . 28 . 2d d vv i n i m = d d v h o a m 4 - = v l o ) l t t ( e g a t l o v w o l t u p t u od n g5 2 0 .5 . 0v i n i m = d d v l o a m 4 = v h i ) l t t ( e g a t l o v h g i h t u p n i0 . 2v v l i ) l t t ( e g a t l o v w o l t u p n id n g8 . 0v i h i ) l t t ( t n e r r u c h g i h t u p n i0 4a v n i x a m = d d v , v 4 . 2 = i l i ) l t t ( t n e r r u c w o l t u p n i0 0 6a v n i x a m = d d v , v 8 . = d d it n e r r u c y l p p u s0 7 50 6 6a mn r e t t a p 0 1 0 1 p d n o i t a p i s s i d r e w o p5 8 . 13 . 2w n r e t t a p 0 1 0 1 v f f i d g n i w s e g a t l o v t u p n i l a i t n e r e f f i d . n i m s t u p n i l c e p l a i t n e r e f f i d r o f 0 0 10 0 6 2v m. 2 2 e r u g i f e e s d v t u o e g a t l o v t u p t u o l a i r e s l a i t n e r e f f i d g n i w s 0 0 4 10 0 6 2v m. 1 2 e r u g i f e e s c n i e c n a t i c a p a c t u p n i3f p table 28. dc characteristics s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us t n e m m o c r e t t i j l a t o tr e t t i j l a t o t t u p t u o a t a d l a i r e s2 9 1s p. k a e p - o t - k a e p t j d r e t t i j c i t s i n i m r e t e d t u p t u o a t a d l a i r e s0 8s p. k a e p - o t - k a e p t r s t , f s e m i t l l a f d n a e s i r t u p t u o a t a d l a i r e s0 0 3s p. 9 1 e r u g i f e e s . % 0 8 - % 0 2 s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us t n e m m o c t k c o l ) y c n e u q e r f ( e m i t k c o l n o i t i s i u q c a y c n e u q e r f ) s p b g 5 2 . 1 ( ) k c o l f o s s o l ( 5 7 1s e l p m a s n r e t t a p e l d i b 0 1 / b 8 . p u t r a t s e c i v e d m o r f , s i s a b t k c o l ) e s a h p ( e s a h p ( e m i t k c o l n o i t i s i u q c a e s a h p ) s p b g 5 2 . 1 ( ) y t i u n i t n o c s i d 0 5 1s n e e s ( e y e a t a d t u p n i % 0 9 . ) 4 2 e r u g i f 0 8 1s n. e y e a t a d t u p n i % 0 7 t j d e c n a r e l o t r e t t i j t u p n i c i t s i n i m r e t e d0 7 3s p r e t t i j t u p n i e c n a r e l o t e c n a r e l o t r e t t i j l a t o t t u p n i a t a d l a i r e s9 9 5s p y b d e i f i c e p s s a , k a e p - o t - k a e p . z 3 . 2 0 8 e e e i r r s r , f s e m i t l l a f d n a e s i r t u p n i a t a d l a i r e s0 3 3s p. 9 1 e r u g i f e e s . % 0 8 - % 0 2 table 26. serial data timing, transmit outputs table 27. serial data timing, receive inputs 31 S2002 dual serial backplane device october 9, 2000 / revision b output load the S2002 serial outputs do not require output pulldown resistors. acquisition time with the input eye diagram shown in figure 24, the S2002 will recover data with a 1e-9 ber within the time specified by t lock in table 27 after an instan- taneous phase shift of the incoming data. figure 22. high speed differential inputs figure 19. serial input/output rise and fall time figure 23. receiver input eye diagram jitter mask figure 20. ttl input/output rise and fall time figure 21. serial output load figure 24. acquisition time eye diagram t r t f 80% 20% 50% 80% 20% 50% t r t f +2.0v +0.8v +2.0v +0.8v 0.01 f 0.01 f v dd -2.3v 100 0.01 f 0.01 f v dd - 1.3 v 1.3 normalized amplitude normalized time 1.0 0.0 0.2 0.3 0.5 0.7 0.8 0.1 0.05 0.6 0.4 0.3 0.7 0.9 0.95 1.0 0.0 bit time amplitude 24% 32 dual serial backplane device S2002 october 9, 2000 / revision b figure 25. loop filter capacitor connections cap1 270 22 nf cap2 270 S2002 33 S2002 dual serial backplane device october 9, 2000 / revision b ordering information x i f e r pe c i v e de g a k c a p t i u c r i c d e t a r g e t n i - s2 0 0 2a g b t 6 5 1 C b t amcc is a registered trademark of applied micro circuits corporation. copyright ? 1999 applied micro circuits corporation amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr., san diego, ca 92121 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1 x xxxx xx prefix device package |
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